The present invention is generally directed to electronic design automation (EDA) for creating integrated circuit (IC) products, such as, for example, system on-chip (SOC) IC products and the like. More specifically, the present invention is directed to providing expeditious timing sign-off verification and correction with minimal fixing and minimal engineering change order (ECO) looping during sign-off of a physical circuit design. In certain applications, the present invention is directed to common path pessimism removal (CPPR) in a timing database to guide optimizer transformations of the circuit design to remedy timing violations detected therein.
While signoff systems and methods are known, such heretofore known systems and methods are encumbered by numerous deficiencies, not the least of which are required repeated transformative iterations between timing signoff and physical implementation/optimization. Other deficiencies include highly divergent timing analyses between timing signoff and physical implementation optimizers—which lead to overly pessimistic timing characteristics and attendant false-positive violations (requiring over-fixing of the circuit design), inordinate turn around time, and overly burdensome storage, processing, and memory requirements. Such deficiencies have heretofore hindered efforts to minimize circuit product fabrication costs, time to market, power requirements, and substrate area while maximizing performance.
There is therefore a need for a system and method for pessimism reduction in timing analysis to guide remedial transformations of a circuit design. There is a need for such system and method which reduce undesirable effects like underclocking or over-fixing due to unwarranted remedial physical corrections of the circuit design for false-positive timing violations of constraints stemming from inadequate CPPR from the circuit design.